Summary:
	"C" (130nm): SledgeHammer, ClawHammer, Newcastle(Odessa, Dublin;; Paris)
	"D" (90nm): Winchester(Oakville, Georgetown, Sonora;; Palermo)
	"E" (90nm): Venice(Albany, Roma;; Palermo)/Manchester, San Diego(Newark, Lancaster; Venus, Troy, Athens)/Toledo(; Denmark, Italy, Egypt)
	"F" (90nm): Orleans(Keene, Richmond;; Manila)/Windsor(Taylor, Trinidad; Santa Ana, Santa Rosa)
	"G" (65nm): Lima(Huron, Sherman)/Brisbane(Tyler)
	"B1" Griffin (65nm): Griffin or Lion(Conesus, Sable)

	Excepting for Winchester which saw a tiny IPC uplift despite officially just
	being a die shrink, all generations perform roughly the same clock for clock
	so performance increases were largely through small clock bumps and
	increasing core count.

Sep 2003:
	- SledgeHammer (Athlon 64 FX, Opteron)
		Socket 940
		1MB L2 Cache
		800MHz HT
		2.2-2.4GHz
		193mm2 die
		Up to 8 processor support

	- ClawHammer (Athlon 64, Athlon 64 FX (2004), Mobile Athlon 64)
		Socket 754/939
		512KB/1MB L2 Cache
		800MHz HT (754)
		1000MHz HT (939)
		1.6-2.6GHz
		193mm2 die
		Socket 939 introduced later as 512KB cache version of SledgeHammer.
		Later fully unlocked with the introduction of ClawHammer FX.
 
Dec 2003:
	- Newcastle (Athlon 64), Odessa (Mobile Athlon 64), Paris (Sempron),
	  Dublin (Mobile Sempron)
		Socket 754/939
		128KB/256KB/512KB L2 Cache
		800MHz HT (754)
		1000MHz HT (939)
		1.6-2.4GHz
		144mm2 die
		Cost reduced ClawHammer (native 512KB cache die).
		AMD64 disabled on Dublin, Paris

Oct 2004:
	- Winchester (Athlon 64), Oakville (Mobile Athlon 64), Palermo (Sempron),
	  Georgetown (Mobile Sempron), Sonora (Mobile Sempron (Low power))
		Socket 754 (Mobile and Sempron)/939
		128KB/256KB/512KB L2 Cache
		800MHz HT (754)
		1000MHz HT (939)
		1.6-2.2GHz
		84mm2 die
		Die shrink from 130nm to 90nm
		Officially just a straight die shrink, but tested 1-7% IPC uplift
		AMD64 disabled on Palermo

Apr 2005:
	- Venice (Athlon 64), Palermo (Sempron), Albany (Mobile Sempron),
	  Roma (Mobile Sempron (Low power))
		Socket 754/939
		128KB/256KB/512KB L2 Cache
		800MHz HT (754/939)
		1000MHz HT (939)
		1.0-2.4GHz
		84mm2 die
		Adds SSE3
		Adds LAHF/SAHF
		No performance uplift
		Improved memory controller
		Yes, AMD reused the Palermo name for Sempron
		AMD64 disabled on E3 stepping Palermo and all Albany, Roma

May 2005:
	- Toledo (Athlon 64 FX, Athlon 64 X2, Athlon 64), Denmark (Opteron),
	  Italy (Opteron), Egypt (Opteron)
		Socket 939/940
		512KB/1MB L2 Cache per core
		1000MHz HT
		1.6-2.8GHz
		199mm2 die
		2 Processor support in Italy
		8 Processor support in Egypt
		Dual core San Diego (or 1MB dual core Venice)

	- Manchester (Athlon 64 X2, Athlon 64)
		Socket 939
		256KB/512KB L2 Cache per core
		1000MHz HT
		2.0-2.4GHz
		147mm2 die
		Dual core Venice (or 512KB version of Toledo)

Jun 2005:
	- San Diego (Athlon 64 FX, Athlon 64), Newark (Mobile Athlon 64),
	  Venus (Opteron), Troy (Opteron), Athens (Opteron),
	  Lancaster (Turion 64 ML/MT)
		Socket 754 (Mobile)/939/940
		512KB/1MB L2 Cache
		800MHz HT (Mobile)
		1000MHz HT
		1.6-3.0GHz
		115mm2 die
		2 Processor support in Troy
		8 Processor support in Athens
		1MB cache version of Venice

May 2006:
	- Orleans (Athlon 64), Manila (Sempron), Keene (Mobile Sempron),
	  Richmond (Turion 64 MK)
		Socket AM2/S1
		128KB/256KB/512KB/1MB L2 Cache
		800MHz HT (Sempron)
		1000MHz HT
		1.6-2.6GHz
		103mm2 die
		Adds AMD-V (Not on Manila, Keene)
		Adds CMPXCHG16B, RDTSCP, CLFLUSH
		Negligible performance increase due to DDR2 (AMD: "Expect about 1%")

	- Windsor (Athlon 64 FX, Athlon 64 X2), Santa Ana (Opteron),
	  Santa Rosa (Opteron), Taylor (Turion 64 X2 TL), Trinidad (Turion 64 X2 TL)
		Socket AM2/F/S1
		256KB/512KB/1MB L2 Cache per core
		800MHz HT (Mobile)
		1000MHz HT
		183mm2 die
		1.8-3.2GHz
		Up to 8 Processor support in Santa Rosa
		Dual core version of Orleans

Jan 2007:
	- Lima (Athlon 64, Athlon LE), Sherman (Athlon Neo TF, Mobile Sempron),
	  Huron (Athlon Neo MV (BGA), Sempron (mobile)), Sparta (Sempron)
		Socket AM2/S1g2 (Mobile)/ASB1 (Mobile BGA)
		256KB/512KB L2 Cache
		800MHz HT (Mobile/Sempron)
		1000MHz HT
		1.0-2.8GHz
		77mm2 die
		Adds Prefetch/PrefetchW (Can run Windows 8.1+)
		No AMD-V on Sparta, Huron (Sempron)
		No significant performance change

	- Brisbane (Athlon 64 X2, Athlon X2, Sempron X2),
	  Tyler (Athlon 64 X2 TK, Turion 64 X2 TL)
		Socket AM2/ASB1 (Mobile BGA)/S1
		256KB (Mobile)/512KB L2 Cache per core
		800MHz HT (Mobile)
		1000MHz HT
		126mm2 die
		1.5-3.1GHz
		Dual core version of Lima
		No AMD-V on Sempron

Jun 2008:
	- Griffin/Lion (Turon X2 Ultra ZM, Turion X2 RM, Athlon X2 QL),
	  Conesus (Athlon Neo X2 L (BGA), Turion Neo X2 L (BGA)),
	  Sable (Athlon QI, Sempron SI)
		Socket S1g2/ASB1 (BGA)
		512KB/1MB L2 Cache per core
		1800-2000MHz HT
		2.0-2.5GHz
		Unknown die size
		Dual core
		Mobile only
		Various uncore improvements from K10, still K8 cores
		No AMD-V on Sable (Sempron)