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CPU Variants/μArch Notes

Overtime I have amassed a decently sized collection of computers, and along with them CPUs. There are many great resources on the net covering every SKU that was ever released from every vendor, but I've always been more interested in the actual dies and the microarchitectures that underly the SKUs. Due to variences in quality, as well as artificial market segmentation, the same piece of silicon is used amongst a whole line up of products. For higher end hardware it's usually easy to correleate a SKU to a codenamed die, but sometimes things aren't so clear. Sometimes the same fundamental microarchitecture gets used under multiple marketing names, sometimes the same marketing name is used for multiple microarchitectures.

This page exists to publish my notes in trying to understand the underlying product for the CPUs I have. It's not meant to be comprehensive but hopefully this information can help others with the same questions I had.

Intel Pentium and Pentium MMX



The original Pentium microarchitecture, known as P5, in desktop form comes in 5 named variants: P5, P54C, P54CQS, P54CS, and P55C. On mobile the Pentium got an additional generation known as "Tillamook." The mobile versions did often have different code names, and the processor specification update indicates that they had some changes for power savings (lacking "DP, APIC, or FRC" and adding "Voltage Reduction Technology").

P5 - 0.8μm

The original P5 is pretty easy to identify as it used the short lived Socket 4 and came in 60MHz and 66MHz variants. Although called short lived Intel did release upgrade CPUs for the socket, but besides the VRM those should be the same as the Socket 5/7 versions and out of scope for this article.

This model had three steppings B1, C1, and D1. The latter two are more common and have the gold heatspreader. With D1 stepping fixing the famous fdiv bug.

P54C - 0.6μm, P54CQS - 0.35μm, P54CS - 0.35μm

The second generation brought with it Socket 5 and a reduction from 5v to 3.3v. This is where things start to become more vague and the official designations become hard to discern. Based on the processor specification update we can begin to decode the stepping names. Specifically note 4 under the basic identification information table states that "The cB1 stepping is logically equivalent to the C2-step, but on a different manufacturing process." This note also tells us that an "m" in the stepping name indicates mobile, and "x" indicates Pentium MMX. (Not explicitly called out by "y" seems to indicate Tillamook.)

The significance of this is that it seems to indicate that we can use the stepping code to determine process node. No letter indicates 0.6μm, "c" indicates 0.35μm, and "y" indicates 0.25μm.

B1, B3, B5 (Model 2, Steppings: 1, 2, 4)
Since these codes indicate only a metal layer change, these are pretty definitively 0.6μm P54C. Released SKUs come in 75, 90, and 100MHz, but the it seems there was also a qualification sample of a 120MHz B5 model.
C2 (Model 2, Stepping 5); mA1 (Same), mA4 (Model 7, Stepping 0)
As the notes say, this is logically equivalent to cB1 which uses a different process node. Given that we can safely assume this is a 0.6μm die. There is some conflicting information around the Internet on if P54CQS refers only to the 0.35μm parts or if it also covers the C2 parts. The C2 stepping comes in 75, 90, 100, 120, and 133MHz (SK098) models. On the mobile side mA4 seems to be similar to C2/mA1 based on errata (and naming scheme) but for some reason identifies as model 7.
cB1 (Model 2, Stepping B); mcB1 (Same)
This is the 0.35μm version of stepping C2 released in 120 and 133MHz (SK106, S106J, SK107, SU038) variants. Given the information we have, this must definitively be P54CQS.
cC0 (Model 2, Stepping C); mcC0 (Same)
Another 0.35μm stepping, but this time coming in 120, 133, 150, 166, and 200MHz variants. Given the availability of higher speed bins and that we've run out of "c" steppings these parts must be P54CS.
E0 (Model 2, Stepping 6)
It's difficult to discern what exactly this stepping is. The naming scheme would suggest that this is a 0.6μm part again, and the errata table shows that it fixes a lot of issues with the previous models. In that sense it's somewhat similar to P54CS, so is it possible that P54CS was back ported to the older process? Models for this stepping come in 75, 90, 100, and 120MHz.

Given that P54C and P54CQS are "logically equivalent" the difference between them is mostly academic, and despite the die shrink the same can likely be said about P54CS vs the E0 stepping. It is interesting to me though that P54CQS is often said as only being 120MHz, but the 133MHz cB1 stepping appears to exist and not particularly hard to find.

P55CS - 0.35μm

Looking at the Pentium MMX, things get a lot simpler. On the desktop there was stepping xA3 (Model 4, Stepping 4) and xB1 (Model 4, Stepping 3). The xA3 stepping comes in 166 and 200MHz models (with 150MHz qualifying sample), while the xB1 came in 166, 200, and 233MHz. On mobile these are mxA3 and mxB1 steppings.

Tillamook - 0.25μm

At the end of the classic Pentium and Pentium MMX lineup is the mobile/embedded only Tillamook. Stepping myA0 (Model 8, Stepping 1) at 166, 200, 233, and 266MHz. Stepping myB2 (Model 8, Stepping 2) at 266 and 300MHz. The embedded version (which uses the same stepping codes) is notable for being Socket 7, although effort is needed to support it in desktop boards.



The information in this section is based on many release reviews from reputable media outlets, such as Anandtech, as well as AMD press releases. I didn't think to write down a list when I originally compiled this info.


From a collector or retro computing point of view the K8 marketing names are a complete disaster. The Athlon 64 reused SKU names multiple times, but this feels like it should matter more than it does in practice. Benchmarks from the release days largely showed little to no IPC improvement generation on generation with the exception of the second generation ("D"), which despite AMD claiming a straight die shrink has been measured by some reviewers to have a 1-7% IPC uplift. The transition to DDR2 with the fourth revision ("F") was officially stated to have a negligible, about 1%, performance uplift. Performance increases were instead a result of increasing clock speeds and eventually adding the second core.

Looking at code names doesn't make things particularly easy either as desktop, mobile, server, and each market segment of each had their own code name. Die configurations started with full cache and native half cache, with dual core variants added to the mix later. For SKUs using one of the cut down dies, there may be an identically specced model with the same name using the larger die with silicon disabled. As a user this shouldn't make a difference outside of overclocking. When it comes to the actual CPU core the letter in the stepping code seems to be the best way to distinguish between them.

The final K8 revision known as either "Griffin" or "Lion" (stepping code B1, family 11h) is mobile only and mixes various uncore improvements from K10 with K8 cores. One specific difference is the increase of HyperTransport to up to 2GHz from the 800MHz-1GHz of normal K8 (family 0fh). After this, in 2009, the "Conesus" platform was released, which is covered by the family 0fh revision guide and seems to be a reversion to the "G" revision core.


C D E F G B1
Year 2003 2004 2005 2006 2007 2008
Process 130nm 90nm 65nm
Socket 940/939/754 939/754 940/939/754 F/AM2/S1 AM2/S1g2 S1g2
Dual core/1M No No 199mm2 183mm2 No ???
Dual core/512K No No 147mm2 No 126mm2 No
Single core/1M 193mm2 No 115mm2 103mm2 No No
Single core/512K 144mm2 84mm2 84mm2 No 77mm2 No
Max frequency 2.6GHz 2.2GHz 3.0GHz 3.2GHz 3.1GHz 2.5GHz
AMD-V No Yes
Prefetch/PrefetchW No Yes

Early Sempron products prior to the E6 stepping had their 64-bit mode disabled. AMD-V, introduced along with the transition to DDR2, was also disabled on Sempron products.

The addition of the Prefetch/PrefetchW instructions in particular is notable since Microsoft started requiring them for Windows 8.1 potentially leaving early K8 users stranded on Windows 8.0 if they had upgraded.

Code names

Rev Cores Cache Code name AMD64 Product Date
C 1 1M SledgeHammer Yes Athlon 64 FX, Opteron Sep 2003
ClawHammer Athlon 64, Athlon 64 FX (2004), Mobile Athlon 64
512K Newcastle Athlon 64 Dec 2003
Odessa Mobile Athlon 64
Paris No Sempron
Dublin Mobile Sempron, Mobile Athlon XP-M
D 1 512K Winchester Yes Athlon 64 Oct 2004
Oakville Mobile Athlon 64
Palermo No Sempron
Georgetown Mobile Sempron
Sonora Mobile Sempron (Low power)
E 2 1M Toledo Yes Athlon 64 FX, Athlon 64 X2, Athlon 64 May 2005
Egypt Opteron (8P)
Italy Opteron (2P)
Denmark Opteron
512K Manchester Athlon 64 X2, Athlon 64
1 1M San Diego Athlon 64 FX, Athlon 64 Jun 2005
Newark Mobile Athlon 64
Athens Opteron (8P)
Troy Opteron (2P)
Venus Opteron
Lancaster Turion 64 ML/MT
512K Venice Athlon 64 Apr 2005
Palermo [Reused] Not E3 Sempron
Albany No Mobile Sempron
Roma Mobile Sempron (Low power)
F 2 1M Windsor Yes Athlon 64 FX, Athlon 64 X2 May 2006
Santa Rosa Opteron (8P/2P)
Santa Ana Opteron
Trinidad Turion 64 X2 TL (256K cache)
Taylor Turion 64 X2 TL
1 1M Orleans Athlon 64
Richmond Turion 64 MK
Manila Sempron
Keene Mobile Sempron
G 2 512K Brisbane Yes Athlon 64 X2, Athlon X2, Sempron X2 Jan 2007
Tyler Athlon 64 X2 TK, Turion 64 X2 TL
Conesus Athlon Neo X2 L (BGA), Turion Neo X2 L (BGA)
1 512K Lima Athlon 64, Athlon LE
Sherman Athlon Neo TF, Mobile Sempron
Huron Athlon Neo MV (BGA), Sempron (mobile)
Sparta Sempron
B1 2 1M Griffin/Lion Yes Turion X2 Ultra ZM, Turion X2 RM, Athlon X2 QL Jun 2008
Sable Athlon QI, Sempron SI

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